| allocation_order_begin(MachineFunction &MF) const | llvm::TargetRegisterClass | [inline, virtual] |
| allocation_order_end(MachineFunction &MF) const | llvm::TargetRegisterClass | [inline, virtual] |
| begin() const | llvm::TargetRegisterClass | [inline] |
| const_iterator typedef | llvm::TargetRegisterClass | |
| contains(unsigned Reg) const | llvm::TargetRegisterClass | [inline] |
| end() const | llvm::TargetRegisterClass | [inline] |
| getAlignment() const | llvm::TargetRegisterClass | [inline] |
| getID() const | llvm::TargetRegisterClass | [inline] |
| getNumRegs() const | llvm::TargetRegisterClass | [inline] |
| getRegister(unsigned i) const | llvm::TargetRegisterClass | [inline] |
| getSize() const | llvm::TargetRegisterClass | [inline] |
| hasSubRegClass(const TargetRegisterClass *cs) const | llvm::TargetRegisterClass | [inline] |
| hasSuperRegClass(const TargetRegisterClass *cs) const | llvm::TargetRegisterClass | [inline] |
| hasType(MVT::ValueType vt) const | llvm::TargetRegisterClass | [inline] |
| iterator typedef | llvm::TargetRegisterClass | |
| sc_iterator typedef | llvm::TargetRegisterClass | |
| subclasses_begin() const | llvm::TargetRegisterClass | [inline] |
| subclasses_end() const | llvm::TargetRegisterClass | [inline] |
| superclasses_begin() const | llvm::TargetRegisterClass | [inline] |
| superclasses_end() const | llvm::TargetRegisterClass | [inline] |
| TargetRegisterClass(unsigned id, const MVT::ValueType *vts, const TargetRegisterClass *const *subcs, const TargetRegisterClass *const *supcs, unsigned RS, unsigned Al, iterator RB, iterator RE) | llvm::TargetRegisterClass | [inline] |
| vt_begin() const | llvm::TargetRegisterClass | [inline] |
| vt_end() const | llvm::TargetRegisterClass | [inline] |
| vt_iterator typedef | llvm::TargetRegisterClass | |
| ~TargetRegisterClass() | llvm::TargetRegisterClass | [inline, virtual] |