LLVM API Documentation

llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

commuteInstruction(MachineInstr *MI) const	llvm::PPCInstrInfo	`[virtual]`
convertToThreeAddress(MachineInstr *TA) const	llvm::TargetInstrInfo	`[inline, virtual]`
get(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
getImplicitDefs(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
getImplicitUses(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
getName(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
getNumOpcodes() const	llvm::TargetInstrInfo	`[inline]`
getNumOperands(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
getPointerRegClass() const	llvm::PPCInstrInfo	`[virtual]`
getRegisterInfo() const	llvm::PPCInstrInfo	`[inline, virtual]`
getSchedClass(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
hasDelaySlot(unsigned Opcode) const	llvm::TargetInstrInfo	`[inline]`
hasVariableOperands(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
INLINEASM enum value	llvm::TargetInstrInfo
insertGoto(MachineBasicBlock &MBB, MachineBasicBlock &TMBB) const	llvm::TargetInstrInfo	`[inline, virtual]`
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::PPCInstrInfo	`[virtual]`
invertPPCBranchOpcode(unsigned Opcode)	llvm::PPCInstrInfo	`[inline, static]`
isBarrier(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isBranch(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isCall(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isCommutableInstr(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isLoad(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo	`[virtual]`
isMoveInstr(const MachineInstr &MI, unsigned &sourceReg, unsigned &destReg) const	llvm::PPCInstrInfo	`[virtual]`
isReturn(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isStore(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo	`[virtual]`
isTerminatorInstr(unsigned Opcode) const	llvm::TargetInstrInfo	`[inline]`
isTwoAddrInstr(MachineOpCode Opcode) const	llvm::TargetInstrInfo	`[inline]`
PHI enum value	llvm::TargetInstrInfo
PPCInstrInfo(PPCTargetMachine &TM)	llvm::PPCInstrInfo
reverseBranchCondition(MachineBasicBlock::iterator MI) const	llvm::TargetInstrInfo	`[inline, virtual]`
TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes)	llvm::TargetInstrInfo
usesCustomDAGSchedInsertionHook(unsigned Opcode) const	llvm::TargetInstrInfo	`[inline]`
~TargetInstrInfo()	llvm::TargetInstrInfo	`[virtual]`