LLVM API Documentation

SparcV9TargetMachine.cpp File Reference

#include "llvm/Function.h"
#include "llvm/PassManager.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/CodeGen/InstrScheduling.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "MappingInfo.h"
#include "MachineFunctionInfo.h"
#include "MachineCodeForInstruction.h"
#include "SparcV9Internals.h"
#include "SparcV9TargetMachine.h"
#include "SparcV9BurgISel.h"
#include "llvm/Support/CommandLine.h"
#include "SparcV9Instr.def"

Include dependency graph for SparcV9TargetMachine.cpp:

Go to the source code of this file.

Namespaces

namespace llvm

Defines

#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS)

Functions

FunctionPass * createMachineCodeConstructionPass (TargetMachine &Target)

FunctionPass * llvm::createSparcV9MachineCodeDestructionPass ()

Variables

static const unsigned ImplicitRegUseList [] = { 0 }

bool llvm::EmitMappingInfo = false

cl::opt< bool > DisableSched ("disable-sched", cl::desc("Disable sparcv9 local scheduling pass"))

cl::opt< bool > DisablePeephole ("disable-peephole", cl::desc("Disable sparcv9 peephole optimization pass"))

cl::opt< bool, true > EmitMappingInfoOpt ("enable-maps", cl::ReallyHidden, cl::location(EmitMappingInfo), cl::init(false), cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"))

cl::opt< bool > EnableModSched ("enable-modsched", cl::desc("Enable modulo scheduling pass"), cl::Hidden)

cl::opt< bool > EnableSBModSched ("enable-modschedSB", cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden)

RegisterTarget< SparcV9TargetMachine > X ("sparcv9"," SPARC V9")

TargetMachine & Target

Define Documentation

#define I	(	ENUM,
		OPCODESTRING,
		NUMOPERANDS,
		RESULTPOS,
		MAXIMM,
		IMMSE,
		NUMDELAYSLOTS,
		LATENCY,
		SCHEDCLASS,
		INSTFLAGS	)

Value:

{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE,             \
          NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0,          \
          ImplicitRegUseList, ImplicitRegUseList, 0 },

Function Documentation

FunctionPass* @182::createMachineCodeConstructionPass ( TargetMachine & Target ) [static]

Definition at line 687 of file SparcV9TargetMachine.cpp.

Variable Documentation

cl::opt<bool> DisablePeephole("disable-peephole", cl::desc("Disable sparcv9 peephole optimization pass")) [static]

cl::opt<bool> DisableSched("disable-sched", cl::desc("Disable sparcv9 local scheduling pass")) [static]

cl::opt<bool, true> EmitMappingInfoOpt("enable-maps", cl::ReallyHidden, cl::location(EmitMappingInfo), cl::init(false), cl::desc("Emit LLVM-to-MachineCode mapping info to assembly")) [static]

cl::opt<bool> EnableModSched("enable-modsched", cl::desc("Enable modulo scheduling pass"), cl::Hidden) [static]

cl::opt<bool> EnableSBModSched("enable-modschedSB", cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden) [static]

const unsigned ImplicitRegUseList[] = { 0 } [static]

Definition at line 34 of file SparcV9TargetMachine.cpp.

TargetMachine& Target

Definition at line 653 of file SparcV9TargetMachine.cpp.

RegisterTarget<SparcV9TargetMachine> X("sparcv9"," SPARC V9") [static]


Namespaces
namespace	llvm
Defines
#define	I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS)
Functions
FunctionPass *	createMachineCodeConstructionPass (TargetMachine &Target)
FunctionPass *	llvm::createSparcV9MachineCodeDestructionPass ()
Variables
static const unsigned	ImplicitRegUseList [] = { 0 }
bool	llvm::EmitMappingInfo = false
cl::opt< bool >	DisableSched ("disable-sched", cl::desc("Disable sparcv9 local scheduling pass"))
cl::opt< bool >	DisablePeephole ("disable-peephole", cl::desc("Disable sparcv9 peephole optimization pass"))
cl::opt< bool, true >	EmitMappingInfoOpt ("enable-maps", cl::ReallyHidden, cl::location(EmitMappingInfo), cl::init(false), cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"))
cl::opt< bool >	EnableModSched ("enable-modsched", cl::desc("Enable modulo scheduling pass"), cl::Hidden)
cl::opt< bool >	EnableSBModSched ("enable-modschedSB", cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden)
RegisterTarget< SparcV9TargetMachine >	X ("sparcv9"," SPARC V9")
TargetMachine &	Target