LLVM API Documentation
#include "SparcV9Internals.h"Include dependency graph for SparcV9SchedInfo.cpp:
Go to the source code of this file.
Variables | |
| static const CPUResource | AllIssueSlots ("All Instr Slots", 4) |
| static const CPUResource | IntIssueSlots ("Int Instr Slots", 3) |
| static const CPUResource | First3IssueSlots ("Instr Slots 0-3", 3) |
| static const CPUResource | LSIssueSlots ("Load-Store Instr Slot", 1) |
| static const CPUResource | CTIIssueSlots ("Ctrl Transfer Instr Slot", 1) |
| static const CPUResource | FPAIssueSlots ("FP Instr Slot 1", 1) |
| static const CPUResource | FPMIssueSlots ("FP Instr Slot 2", 1) |
| static const CPUResource | IAluN ("Int ALU 1or2", 2) |
| static const CPUResource | IAlu0 ("Int ALU 1", 1) |
| static const CPUResource | IAlu1 ("Int ALU 2", 1) |
| static const CPUResource | LSAluC1 ("Load/Store Unit Addr Cycle", 1) |
| static const CPUResource | LSAluC2 ("Load/Store Unit Issue Cycle", 1) |
| static const CPUResource | LdReturn ("Load Return Unit", 1) |
| static const CPUResource | FPMAluC1 ("FP Mul/Div Alu Cycle 1", 1) |
| static const CPUResource | FPMAluC2 ("FP Mul/Div Alu Cycle 2", 1) |
| static const CPUResource | FPMAluC3 ("FP Mul/Div Alu Cycle 3", 1) |
| static const CPUResource | FPAAluC1 ("FP Other Alu Cycle 1", 1) |
| static const CPUResource | FPAAluC2 ("FP Other Alu Cycle 2", 1) |
| static const CPUResource | FPAAluC3 ("FP Other Alu Cycle 3", 1) |
| static const CPUResource | IRegReadPorts ("Int Reg ReadPorts", INT_MAX) |
| static const CPUResource | IRegWritePorts ("Int Reg WritePorts", 2) |
| static const CPUResource | FPRegReadPorts ("FP Reg Read Ports", INT_MAX) |
| static const CPUResource | FPRegWritePorts ("FP Reg Write Ports", 1) |
| static const CPUResource | CTIDelayCycle ("CTI delay cycle", 1) |
| static const CPUResource | FCMPDelayCycle ("FCMP delay cycle", 1) |
| static const InstrClassRUsage | NoneClassRUsage |
| static const InstrClassRUsage | IEUNClassRUsage |
| static const InstrClassRUsage | IEU0ClassRUsage |
| static const InstrClassRUsage | IEU1ClassRUsage |
| static const InstrClassRUsage | FPMClassRUsage |
| static const InstrClassRUsage | FPAClassRUsage |
| static const InstrClassRUsage | LDClassRUsage |
| static const InstrClassRUsage | STClassRUsage |
| static const InstrClassRUsage | CTIClassRUsage |
| static const InstrClassRUsage | SingleClassRUsage |
| static const InstrClassRUsage | SparcV9RUsageDesc [] |
| static const InstrIssueDelta | SparcV9InstrIssueDeltas [] |
| static const InstrRUsageDelta | SparcV9InstrUsageDeltas [] |
const CPUResource AllIssueSlots("All Instr Slots", 4) [static] |
const InstrClassRUsage CTIClassRUsage [static] |
Initial value:
{
SPARC_CTI,
7,
1,
false,
false,
0,
4,
{ 0, 1, 2, 3 },
4,
{
{ AllIssueSlots.rid, 0, 1 },
{ CTIIssueSlots.rid, 0, 1 },
{ IAlu0.rid, 1, 1 },
{ CTIDelayCycle.rid, 1, 2 }
}
}
Definition at line 345 of file SparcV9SchedInfo.cpp.
const CPUResource CTIDelayCycle("CTI delay cycle", 1) [static] |
const CPUResource CTIIssueSlots("Ctrl Transfer Instr Slot", 1) [static] |
const CPUResource FCMPDelayCycle("FCMP delay cycle", 1) [static] |
const CPUResource First3IssueSlots("Instr Slots 0-3", 3) [static] |
const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1) [static] |
const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1) [static] |
const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1) [static] |
const InstrClassRUsage FPAClassRUsage [static] |
Initial value:
{
SPARC_FPA,
7,
1,
false,
false,
0,
4,
{ 0, 1, 2, 3 },
7,
{
{ AllIssueSlots.rid, 0, 1 },
{ FPAIssueSlots.rid, 0, 1 },
{ FPRegReadPorts.rid, 1, 1 },
{ FPAAluC1.rid, 2, 1 },
{ FPAAluC2.rid, 3, 1 },
{ FPAAluC3.rid, 4, 1 },
{ FPRegWritePorts.rid, 6, 1 }
}
}
Definition at line 267 of file SparcV9SchedInfo.cpp.
const CPUResource FPAIssueSlots("FP Instr Slot 1", 1) [static] |
const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1) [static] |
const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1) [static] |
const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1) [static] |
const InstrClassRUsage FPMClassRUsage [static] |
Initial value:
{
SPARC_FPM,
7,
1,
false,
false,
0,
4,
{ 0, 1, 2, 3 },
7,
{
{ AllIssueSlots.rid, 0, 1 },
{ FPMIssueSlots.rid, 0, 1 },
{ FPRegReadPorts.rid, 1, 1 },
{ FPMAluC1.rid, 2, 1 },
{ FPMAluC2.rid, 3, 1 },
{ FPMAluC3.rid, 4, 1 },
{ FPRegWritePorts.rid, 6, 1 }
}
}
Definition at line 242 of file SparcV9SchedInfo.cpp.
const CPUResource FPMIssueSlots("FP Instr Slot 2", 1) [static] |
const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX) [static] |
const CPUResource FPRegWritePorts("FP Reg Write Ports", 1) [static] |
const CPUResource IAlu0("Int ALU 1", 1) [static] |
const CPUResource IAlu1("Int ALU 2", 1) [static] |
const CPUResource IAluN("Int ALU 1or2", 2) [static] |
const InstrClassRUsage IEU0ClassRUsage [static] |
Initial value:
{
SPARC_IEU0,
7,
1,
false,
false,
0,
3,
{ 0, 1, 2 },
5,
{
{ AllIssueSlots.rid, 0, 1 },
{ IntIssueSlots.rid, 0, 1 },
{ IAluN.rid, 1, 1 },
{ IAlu0.rid, 1, 1 },
{ IRegWritePorts.rid, 6, 1 }
}
}
Definition at line 190 of file SparcV9SchedInfo.cpp.
const InstrClassRUsage IEU1ClassRUsage [static] |
Initial value:
{
SPARC_IEU1,
7,
1,
false,
false,
0,
3,
{ 0, 1, 2 },
5,
{
{ AllIssueSlots.rid, 0, 1 },
{ IntIssueSlots.rid, 0, 1 },
{ IAluN.rid, 1, 1 },
{ IAlu1.rid, 1, 1 },
{ IRegWritePorts.rid, 6, 1 }
}
}
Definition at line 216 of file SparcV9SchedInfo.cpp.
const InstrClassRUsage IEUNClassRUsage [static] |
Initial value:
{
SPARC_IEUN,
7,
3,
false,
false,
0,
3,
{ 0, 1, 2 },
4,
{
{ AllIssueSlots.rid, 0, 1 },
{ IntIssueSlots.rid, 0, 1 },
{ IAluN.rid, 1, 1 },
{ IRegWritePorts.rid, 6, 1 }
}
}
Definition at line 165 of file SparcV9SchedInfo.cpp.
const CPUResource IntIssueSlots("Int Instr Slots", 3) [static] |
const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX) [static] |
const CPUResource IRegWritePorts("Int Reg WritePorts", 2) [static] |
const InstrClassRUsage LDClassRUsage [static] |
Initial value:
{
SPARC_LD,
7,
1,
false,
false,
0,
3,
{ 0, 1, 2, },
6,
{
{ AllIssueSlots.rid, 0, 1 },
{ First3IssueSlots.rid, 0, 1 },
{ LSIssueSlots.rid, 0, 1 },
{ LSAluC1.rid, 1, 1 },
{ LSAluC2.rid, 2, 1 },
{ LdReturn.rid, 2, 1 },
{ IRegWritePorts.rid, 6, 1 }
}
}
Definition at line 292 of file SparcV9SchedInfo.cpp.
const CPUResource LdReturn("Load Return Unit", 1) [static] |
const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1) [static] |
const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1) [static] |
const CPUResource LSIssueSlots("Load-Store Instr Slot", 1) [static] |
const InstrClassRUsage NoneClassRUsage [static] |
Initial value:
{
SPARC_NONE,
7,
4,
false,
false,
0,
4,
{ 0, 1, 2, 3 },
0,
{
}
}
Definition at line 141 of file SparcV9SchedInfo.cpp.
const InstrClassRUsage SingleClassRUsage [static] |
Initial value:
{
SPARC_SINGLE,
7,
1,
true,
false,
0,
1,
{ 0 },
5,
{
{ AllIssueSlots.rid, 0, 1 },
{ AllIssueSlots.rid, 0, 1 },
{ AllIssueSlots.rid, 0, 1 },
{ AllIssueSlots.rid, 0, 1 },
{ IAlu0.rid, 1, 1 }
}
}
Definition at line 371 of file SparcV9SchedInfo.cpp.
const InstrIssueDelta SparcV9InstrIssueDeltas[] [static] |
Definition at line 422 of file SparcV9SchedInfo.cpp.
const InstrRUsageDelta SparcV9InstrUsageDeltas[] [static] |
Definition at line 512 of file SparcV9SchedInfo.cpp.
const InstrClassRUsage SparcV9RUsageDesc[] [static] |
Initial value:
{
NoneClassRUsage,
IEUNClassRUsage,
IEU0ClassRUsage,
IEU1ClassRUsage,
FPMClassRUsage,
FPAClassRUsage,
CTIClassRUsage,
LDClassRUsage,
STClassRUsage,
SingleClassRUsage
}
Definition at line 399 of file SparcV9SchedInfo.cpp.
const InstrClassRUsage STClassRUsage [static] |
Initial value:
{
SPARC_ST,
7,
1,
false,
false,
0,
3,
{ 0, 1, 2 },
4,
{
{ AllIssueSlots.rid, 0, 1 },
{ First3IssueSlots.rid, 0, 1 },
{ LSIssueSlots.rid, 0, 1 },
{ LSAluC1.rid, 1, 1 },
{ LSAluC2.rid, 2, 1 }
}
}
Definition at line 319 of file SparcV9SchedInfo.cpp.