# frv testcase for nfmss $FRi,$FRj,$FRk # mach: fr500 fr550 frv .include "testutils.inc" float_constants start load_float_constants load_float_constants1 .global nfmss nfmss: nfmss fr16,fr4,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr8,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr28 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr12,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr16,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr16 test_fr_fr fr3,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr20,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr16 test_fr_fr fr3,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr24,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr28,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr8 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr32,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr36,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr40,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr44,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr16,fr48,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr4,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr8,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr28 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr12,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr16,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr16 test_fr_fr fr3,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr20,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr16 test_fr_fr fr3,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr24,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr28,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr8 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr32,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr36,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr40,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr44,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr20,fr48,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr0,fr2 test_fr_fr fr2,fr0 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr4,fr2 test_fr_fr fr2,fr4 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr8,fr2 test_fr_fr fr2,fr8 test_fr_fr fr3,fr32 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr12,fr2 test_fr_fr fr2,fr12 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr16,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr28 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr20,fr2 test_fr_fr fr2,fr16 test_fr_fr fr2,fr20 test_fr_fr fr3,fr28 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr24,fr2 test_fr_fr fr2,fr24 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr28,fr2 test_fr_fr fr2,fr28 test_fr_fr fr3,fr20 test_fr_fr fr3,fr16 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr32,fr2 test_fr_fr fr2,fr32 test_fr_fr fr3,fr8 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr36,fr2 test_fr_fr fr2,fr36 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr40,fr2 test_fr_fr fr2,fr40 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr44,fr2 test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr48,fr2 test_fr_fr fr2,fr48 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr52,fr2 test_fr_fr fr2,fr52 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr28,fr8,fr2 test_fr_fr fr2,fr8 test_fr_fr fr3,fr32 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr8,fr28,fr2 test_fr_fr fr2,fr8 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr32,fr36,fr2 test_fr_fr fr2,fr40 test_fr_fr fr3,fr8 test_spr_immed 0,fner1 test_spr_immed 0,fner0 ; try to cause exceptions nfmss fr4,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr0,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr56,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr60,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0x6,fner1 test_spr_immed 0,fner0 set_spr_immed 0,fner0 set_spr_immed 0,fner1 nfmss fr48,fr32,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr52,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr56,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0,fner1 test_spr_immed 0,fner0 nfmss fr60,fr28,fr1 ; test_fr_fr fr1,fr44 ; test_fr_fr fr2,fr44 test_spr_immed 0x6,fner1 test_spr_immed 0,fner0 pass